你如何在Verilog或VHDL中实现这个数字逻辑?

I posted an answer to another * question which requires some digital logic to be implemented in Verilog or VHDL so that it can be programmed into an FPGA.

我发布了另一个*问题的答案，这个问题需要在Verilog或VHDL中实现一些数字逻辑，这样它就可以被编程成FPGA。

How would you implement the following logic diagram in Verilog, VHDL, or any other hardware description language?

您将如何在Verilog、VHDL或其他硬件描述语言中实现以下逻辑关系图?

The numbered boxes represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read back into that same computer system.

编号的方框表示字段中的位。每个字段都有K位，当前和掩码的位将由计算机系统提供(使用锁存寄存器或等效项)。下一个字节将被读入相同的计算机系统。

alt text http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg

alt文本http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg

1 个解决方案

#1

Something like this?

是这样的吗?

module scheduler
 #( parameter K = 10 )
  (
   input wire [K:1] current,
   input wire [K:1] mask,
   output reg [K:1] next
   );

   reg [K:1] a;
   reg [K:1] b;

   //'[i+1]' busses that wrap.
   // eg, for a 4-bit bus...
   // a[i]:        a[4],a[3],a[2],a[1] (obviously...)
   // a_wrap[i]:   a[1],a[4],a[3],a[2] 
   wire [K:1] mask_wrap    = { mask[1],mask[K:2] };
   wire [K:1] a_wrap       = { a[1], a[K:2] };
   wire [K:1] current_wrap = { current[1], current[K:2] };

   integer i;
   always @( * ) begin
      for( i=1; i<=K; i=i+1 ) begin
         a[i] = ~current_wrap[i] && b[i];
         b[i] = a_wrap[i] || mask_wrap[i];
         next[i] = ~a[i] && mask_wrap[i];
      end
   end


endmodule

(Disclaimer: linted but not simulated)

(免责声明:linted但不模拟)

#1