如何在Verilog中为for循环中的寄存器添加值？

I am currently trying to make a simple up counter inside of Verilog where the counter increases by 1 whenever i come across a '1' in an 8-bit stream. So for example with the 8-bit in put 8'b11001100, the output register would be 4'b0100. I created a for loop to pass through the 8-bit stream to see whenever i come across a '1' but whenever i try to add 1 to my register i get very odd assigning errors i have never seen before. Any help would be appreciated! Here is my source.

我目前正在尝试在Verilog内部创建一个简单的向上计数器,每当我在8位流中遇到“1”时,计数器就会增加1。因此,例如8位输入8'b11001100,输出寄存器为4'b0100。我创建了一个for循环来通过8位流来查看每当我遇到'1'时,但每当我尝试将1添加到我的寄存器时,我会得到非常奇怪的分配错误,这是我以前从未见过的。任何帮助,将不胜感激!这是我的来源。

module stream_counter(stream);

input[7:0] stream;
output[3:0] stream_counter;

reg[3:0] stream_counter;
genvar index;
genvar counter;

always @ (stream)
counter = 0;

for(index = 0; index < 8; index = index +1) begin
    if(stream[index]) begin
        counter = counter + 1;
    end
end 
end 

assign stream_counter = counter;
endmodule

The errors i am getting when compiling are:

我在编译时遇到的错误是:

** Error: (vlog-13069) stream_counter.v(15): near "=": syntax error, unexpected '='.

**错误:(vlog-13069)stream_counter.v(15):near“=”:语法错误,意外'='。

** Error: stream_counter.v(15): (vlog-13205) Syntax error found in the scope following 'counter'. Is there a missing '::'?

**错误:stream_counter.v(15):( vlog-13205)在'counter'后面的范围内发现语法错误。缺少'::'吗?

1 个解决方案

#1

At first glance you're missing a begin after the first always block declaration. And I would use an asterisk to let the tool manage the sensitivity list. For example:

乍一看,在第一个始终阻止声明后,你错过了一个开头。我会使用星号让工具管理敏感度列表。例如:

always @ (*) begin
...