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文件名称：微处理器体系架构
文件大小：13.5MB
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更新时间：2021-09-15 14:24:52
微处理器 体系架构 微架构
1 Introduction ...........................................1
1.1 A Quick View of Technological Advances 2
1.2 Performance Metrics 6
1.3 Performance Evaluation 12
1.4 Summary 22
1.5 Further Reading and Bibliographical Notes 23
exercises 24 references 28
2 TheBasics............................................29
2.1 Pipelining 29
2.2 Caches 46
2.3 Virtual Memory and Paging 59
2.4 Summary 68
2.5 Further Reading and Bibliographical Notes 68
exercises 69 references 73
3 SuperscalarProcessors ...................................75
3.1 From Scalar to Superscalar Processors 75
3.2 Overview of the Instruction Pipeline of the DEC Alpha 21164 78
3.3 Introducing Register Renaming, Reorder Buffer, and
Reservation Stations 89
3.4 Overview of the Pentium P6 Microarchitecture 102
3.5 VLIW/EPIC Processors 111
3.6 Summary 121
3.7 Further Reading and Bibliographical Notes 122
exercises 124 references 126
4
Front-End:BranchPrediction,InstructionFetching,andRegister Renaming ...........................................129
4.1 Branch Prediction 130 Sidebar: The DEC Alpha 21264 Branch Predictor 157
4.2 Instruction Fetching 158
4.3 Decoding 164
4.4 Register Renaming (a Second Look) 165
4.5 Summary 170
4.6 Further Reading and Bibliographical Notes 170
exercises 171 Programming Projects 174 references 174
Back-End:InstructionScheduling,MemoryAccessInstructions,
and Clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.1 Instruction Issue and Scheduling (Wakeup and Select) 178
5.2 Memory-Accessing Instructions 184
5.3 Back-End Optimizations 195
5.4 Summary 203
5.5 Further Reading and Bibliographical Notes 204
exercises 205
Programming Project 206 references 206
5
6 TheCacheHierarchy ...................................208
6.1 Improving Access to L1 Caches 209
6.2 Hiding Memory Latencies 218
6.3 Design Issues for Large Higher-Level Caches 232
6.4 Main Memory 245
6.5 Summary 253
6.6 Further Reading and Bibliographical Notes 254
exercises 255
Programming Projects 257 references 258
7 Multiprocessors .......................................260
7.1 Multiprocessor Organization 261
7.2 Cache Coherence 269
7.3 Synchronization 281
7.4 Relaxed Memory Models 290
7.5 Multimedia Instruction Set Extensions 294
7.6 Summary 296
7.7 Further Reading and Bibliographical Notes 297
exercises 298 references 3008 Multithreadingand(Chip)Multiprocessing ...................
8.1 Single-Processor Multithreading
8.2 General-Purpose Multithreaded Chip Multiprocessors
8.3 Special-Purpose Multithreaded Chip Multiprocessors
8.4 Summary
8.5 Further Reading and Bibliographical Notes
exercises references
9 CurrentLimitationsandFutureChallenges ...................
9.1 Power and Thermal Management
9.2 Technological Limitations: Wire Delays and Pipeline Depths
9.3 Challenges for Chip Multiprocessors
9.4 Summary
9.5 Further Reading and Bibliographical Notes
references