A fast method for timing verification that uses the conditions that cause changes in the output values of gates

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文件名称：A fast method for timing verification that uses the conditions that cause changes in the output values of gates
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更新时间：2021-06-29 17:19:47
学术 论文 A fast method for timing verification that uses the conditions that cause changes in the output values of gates A Fast Method for Timing Verification that Uses the Conditions that Cause Changes in the Output Values of Gates Atsushi Ohnishi 1 and Yuji Sugiyama 2 1 Department of Electronics and Computer Engineering, Tsuyama National College of Technology, Tsuyama, Japan 708-8509 2 Department of Information Technology, Faculty of Engineering, Okayama University, Okayama, Japan 700-8530 SUM