【文件属性】：
文件名称：verilog FSM 范例
文件大小：6KB
文件格式：V
更新时间：2017-02-14 17:16:57
fsm
verilog FSM 范例
//FSM
always @(posedge clk or negedge rst_n)begin
if(rst_n == 1'd0)begin
sta_curr <= S_IDLE;
end
else begin
sta_curr <=#U_DLY sta_next;
end
end
always @(*)begin
case(sta_curr)
S_IDLE:begin
if(s_idle_jump==1'd1)
sta_next = S_PRE_DLY;
else
sta_next = S_IDLE;
end
S_PRE_DLY:begin
if(s_pre_dly_jump==1'd1)
sta_next = S_WAIT_LE;
else
sta_next = S_PRE_DLY;
end