FPGA器件实现乘法器

【文件属性】：
文件名称：FPGA器件实现乘法器
文件大小：1.15MB
文件格式：PDF
更新时间：2012-05-06 11:57:16
Cyclone II devices have embedded Stratix® II, Stratix, Stratix GX, Cyclone™ II, and Cyclone devices have dedicated architectural features that make it easy to implement highperformance multipliers. Stratix II, Stratix, and Stratix GX devices feature embedded high-performance multiplier-accumulators (MACs) in dedicated digital signal processing (DSP) blocks. DSP blocks can operate at data rates above 300 million samples per second (MSPS), making Stratix II, Stratix, and Stratix GX devices ideal for high-speed DSP applications. Cyclone II devices have embedded multiplier blocks for DSP. In addition to the dedicated DSP blocks, designers can also use the Stratix II, Stratix, and Stratix GX devices’ TriMatrix™ memory blocks to implement high-performance soft multipliers of variable depths and widths. For example, designers can useTriMatrix memory blocks as lookup tables (LUTs) that contain partial results from multiplication of input data with coefficients. Cyclone II and Cyclone devices have M4K memory blocks which can be used as LUTs to implement variable depth/width high-performance soft multipliers for low cost, high volume DSP applications.