18bit serdes design guide

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文件名称：18bit serdes design guide
文件大小：2.82MB
文件格式：PDF
更新时间：2015-05-11 03:15:38
serdes design, architecture The DS92LV18 and SCAN921821 are members of National’s robust and easyto- use Bus LVDS serializer/deserializer (SerDes) family already popular in a wide variety of telecom, datacom, industrial, and commercial backplane/cable interconnect applications. They are similar to the original 10- and 16- bit Bus LVDS SerDes products, but provide a wider, 18-bit data bus payload to support not only byte-oriented data but also carry other information such as parity, frame, control, status, sync, low frequency bus or clock signals, etc. The DS92LV18 and SCAN921821 are very flexible and performs over a wide, 15 - 66 MHz frequency range. Both the transmit clock and receiver reference clock have high jitter tolerance, allowing the use of low cost clock sources. The DS92LV18 serializer and deserializer sections are fully independent and can be operated at different frequencies. This is useful when upstream and downstream rates are not balanced. The SCAN921821 is a dual transmitter that features programmable pre-emphasis to drive long cables . The DS92LV18 receiver locks to random data, eliminating the need to interrupt normal traffic with PLL training patterns after hot plug events. The usual lossof- lock feedback path from receiver to transmitter is also not required. Line and local loopback test modes allow the designer to segregate portions of the system to facilitate system diagnostics.