【文件属性】:
文件名称:dnn-rtl:DNN的Verilog RTL实现
文件大小:58.45MB
文件格式:ZIP
更新时间:2021-05-10 19:22:32
SystemVerilog
dnn-RTL
USC DNN系统的RTL和FPGA实现-Sourya,Yinan,Chiye,Mahdi
testbench-主文件是tb_mnist.v。 其他文件用于婴儿网络或子模块。
src-所有源代码Verilog文件。 等级制度:
DNN.v - whole network
layer_block.v - Contains processors, memory, state machines and other small logic for each layer
memory_ctr.v - State machine for each layer. Generates control signals for memory (address, enable), counter and mux
processor_set.v - FF, BP and UP proces