VHDL信号的多维数组

时间:2022-12-17 00:10:14

I have a signal in VHDL declared like this :

我在VHDL中有一个信号声明如下:

signal Temp_Key : std_logic_vector(79 downto 0);

This Temp_Key is passed through a for loop 31 times and it is modified. I want to store all the 31 different Temp_Keys in an array.

此Temp_Key通过for循环传递31次并进行修改。我想将31个不同的Temp_Keys存储在一个数组中。

Is it possible to use multi-dimensional arrays in VHDL to store 80 bit signals ?

是否可以在VHDL中使用多维数组来存储80位信号?

3 个解决方案

#1


19  

Yes, first you need to declare a type:

是的,首先你需要声明一个类型:

type YOUR_ARRAY_TYPE is array (0 to 30) of std_logic_vector(79 downto 0);

Note you can also declare the type to be of undefined length - so you can specify how many 80 bit words it has when you declare your signal. And with VHDL 2008, you can also leave the size of the slv unspecified, also to be declared when you create your signal. For example:

注意,您也可以声明类型为未定义的长度 - 因此您可以指定声明信号时它具有多少80位字。使用VHDL 2008,您还可以保留未指定的slv的大小,也可以在创建信号时声明。例如:

type slv_array is array (natural range <>) of std_logic_vector;

and then use it

然后使用它

signal MY_SIGNAL : YOUR_ARRAY_TYPE;
...
MY_SIGNAL(0) <= data;
...
MY_SIGNAL(1) <= data;

See here for a reference.

请参阅此处以供参考。

#2


0  

Like the post above says, you can create any multi-dimensional array datatype. The other thing you need to be careful about is whether this code is synthesizable (i.e. targeted to FPGAs or ASICs, or is it purely for simulation). You can iterate from 0 to 31 using an FSM/counter or a generate block depending on how critical your timing is and how much area you are willing to use. A multi-dimensional array instance shown in above post is certainly synthesizable.

与上面的帖子一样,您可以创建任何多维数组数据类型。您需要注意的另一件事是这个代码是否是可合成的(即针对FPGA或ASIC,还是纯粹用于模拟)。您可以使用FSM /计数器或生成块从0到31进行迭代,具体取决于您的时间安排的重要程度以及您愿意使用的区域。上面帖子中显示的多维数组实例肯定是可合成的。

#3


0  

In VHDL there are two options

在VHDL中有两种选择

Option 1

signal X is array (range) of ArrayType;

Option 2

signal Y is array (range1, range2) of Type;

I think that option 1 is better supported by the tools. I also find similarity between these two options and the functional programming that teaches us that we can always curry a multivariate function (x,y) into a chain of single parameter ones, f(x) -> f(y). The latter looks like array of arrays.

我认为工具可以更好地支持选项1。我还发现这两个选项和函数式编程之间的相似性告诉我们,我们总是可以将多元函数(x,y)变成一个单参数链f(x) - > f(y)。后者看起来像数组的数组。

#1


19  

Yes, first you need to declare a type:

是的,首先你需要声明一个类型:

type YOUR_ARRAY_TYPE is array (0 to 30) of std_logic_vector(79 downto 0);

Note you can also declare the type to be of undefined length - so you can specify how many 80 bit words it has when you declare your signal. And with VHDL 2008, you can also leave the size of the slv unspecified, also to be declared when you create your signal. For example:

注意,您也可以声明类型为未定义的长度 - 因此您可以指定声明信号时它具有多少80位字。使用VHDL 2008,您还可以保留未指定的slv的大小,也可以在创建信号时声明。例如:

type slv_array is array (natural range <>) of std_logic_vector;

and then use it

然后使用它

signal MY_SIGNAL : YOUR_ARRAY_TYPE;
...
MY_SIGNAL(0) <= data;
...
MY_SIGNAL(1) <= data;

See here for a reference.

请参阅此处以供参考。

#2


0  

Like the post above says, you can create any multi-dimensional array datatype. The other thing you need to be careful about is whether this code is synthesizable (i.e. targeted to FPGAs or ASICs, or is it purely for simulation). You can iterate from 0 to 31 using an FSM/counter or a generate block depending on how critical your timing is and how much area you are willing to use. A multi-dimensional array instance shown in above post is certainly synthesizable.

与上面的帖子一样,您可以创建任何多维数组数据类型。您需要注意的另一件事是这个代码是否是可合成的(即针对FPGA或ASIC,还是纯粹用于模拟)。您可以使用FSM /计数器或生成块从0到31进行迭代,具体取决于您的时间安排的重要程度以及您愿意使用的区域。上面帖子中显示的多维数组实例肯定是可合成的。

#3


0  

In VHDL there are two options

在VHDL中有两种选择

Option 1

signal X is array (range) of ArrayType;

Option 2

signal Y is array (range1, range2) of Type;

I think that option 1 is better supported by the tools. I also find similarity between these two options and the functional programming that teaches us that we can always curry a multivariate function (x,y) into a chain of single parameter ones, f(x) -> f(y). The latter looks like array of arrays.

我认为工具可以更好地支持选项1。我还发现这两个选项和函数式编程之间的相似性告诉我们,我们总是可以将多元函数(x,y)变成一个单参数链f(x) - > f(y)。后者看起来像数组的数组。