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此系列的文章前提：熟悉uboot启动流程；如果不熟悉请先看我的另一篇博文：x210v3开发板u-boot-2012.10移植之补充篇---uboot启动流程详解
从前面的IROM启动知道，其实时钟已经配置过了，主频是800M。不过这里我们为了获得更好的性能，让开发板运行在主频1000MHz下。
直接进入主题修改board/samsung/x210v3/lowlevel_init.S
首先，明确任务：这个文件干了些啥？我总结了一下，
1.芯片选择；2.关中断；3.初始化系统时钟； 4.初始化串口；5.初始化内存。
1.芯片选择
这里我们只用到一块芯片，不用选择直接去掉相关代码，那么怎么去掉呢？先搞清楚代码是如何进行芯片选择的？下面分析下代码
/* r5 has always zero */
mov r5, #0
ldr r7, =S5PC100_GPIO_BASE
ldr r8, =S5PC100_GPIO_BASE
/* Read CPU ID */
ldr r2, =S5PC110_PRO_ID
ldr r0, [r2]
mov r1, #0x00010000
and r0, r0, r1
cmp r0, r5
beq 100f
ldr r8, =S5PC110_GPIO_BASE
100:
再次强调s5pv210和s5pc110的寄存器是相同的。r5的值始终是0，然后一看下面奇怪了，r7和r8的值是一样的，都是s5pc100的GPIO的基地址，有古怪。接着分析，有注释就是好，一看就知道在读芯片ID，读到r0，然后取出r0的第16位（从第0位开始）看是不是0，如果是0跳转到标号100，编号100是执行s5pc100的代码。你不要跟我说是跳转到标号100f，f表示往前面跳转，front的缩写嘛。那么显然往回跳呢？你应该可以猜到，b，back的意思。如果不是0呢？将s5pc110的GPIO基地址赋值给r8。现在应该清楚了，r7如果等于r8就说明是s5pc100芯片；r7不等于r8说明是s5pc110芯片。说是这么说，那么芯片ID寄存器的第16位是多少呢？看datasheet，确实是1.所以带了beq的代码尽情删除吧。前面的判断代码也不用了，r7也不要，直接用r8作为GPIO基地址。
经过删除后的代码如下：
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/power.h>
/*
* Register usages:
*
* r5 has zero always
* r7 has S5PC100 GPIO base, 0xE0300000
* r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
* r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
*/
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
mov r11, lr
/* r5 has always zero */
mov r5, #0
ldr r8, =S5PC110_GPIO_BASE
/* Disable Watchdog */
ldr r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
str r5, [r0]
/* S5PC100 has 3 groups of interrupt sources */
ldr r0, =S5PC110_VIC0_BASE @ 0xF2000000
add r1, r0, #0x00100000
add r2, r0, #0x00200000
/* Disable all interrupts (VIC0, VIC1 and VIC2) */
mvn r3, #0x0
str r3, [r0, #0x14] @ INTENCLEAR
str r3, [r1, #0x14] @ INTENCLEAR
str r3, [r2, #0x14] @ INTENCLEAR
/* Set all interrupts as IRQ */
str r5, [r0, #0xc] @ INTSELECT
str r5, [r1, #0xc] @ INTSELECT
str r5, [r2, #0xc] @ INTSELECT
/* Pending Interrupt Clear */
str r5, [r0, #0xf00] @ INTADDRESS
str r5, [r1, #0xf00] @ INTADDRESS
str r5, [r2, #0xf00] @ INTADDRESS
/* for UART */
bl uart_init
bl internal_ram_init
/* Clear wakeup status register */
ldr r0, =S5PC110_WAKEUP_STAT
ldr r1, [r0]
str r1, [r0]
/* IO retension release */
ldr r0, =S5PC110_OTHERS @ 0xE010E000
ldr r1, [r0]
ldr r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
orr r1, r1, r2
str r1, [r0]
b 1f
didle_wakeup:
/* Wait when APLL is locked */
ldr r0, =0xE0100100 @ S5PC110_APLL_CON
lockloop:
ldr r1, [r0]
and r1, r1, #(1 << 29)
cmp r1, #(1 << 29)
bne lockloop
ldr r0, =S5PC110_INFORM0
ldr r1, [r0]
mov pc, r1
nop
nop
nop
nop
nop
1:
mov lr, r11
mov pc, lr
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
/* Set OSC_FREQ value */
ldr r1, =0xf
str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
/* Set MTC_STABLE value */
ldr r1, =0xffffffff
str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
/* Set CLAMP_STABLE value */
ldr r1, =0x3ff03ff
str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
/* Set Clock divider */
ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
str r1, [r0, #0x300]
ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
str r1, [r0, #0x310]
/* Set Lock Time */
ldr r1, =0x2cf @ Locktime : 30us
str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
/* S5PC110_APLL_CON */
ldr r1, =0x80C80601 @ 800MHz
str r1, [r0, #0x100]
/* S5PC110_MPLL_CON */
ldr r1, =0x829B0C01 @ 667MHz
str r1, [r0, #0x108]
/* S5PC110_EPLL_CON */
ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
str r1, [r0, #0x110]
/* S5PC110_VPLL_CON */
ldr r1, =0x806C0603 @ 54MHz
str r1, [r0, #0x120]
/* Set Source Clock */
ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
/* OneDRAM(DMC0) clock setting */
ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
/* XCLKOUT = XUSBXTI 24MHz */
add r2, r0, #0xE000 @ S5PC110_OTHERS
ldr r1, [r2]
orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
str r1, [r2]
/* CLK_IP0 */
ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
str r1, [r0, #0x460] @ S5PC110_CLK_IP0
/* CLK_IP1 */
ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
@ NANDXL[24]
str r1, [r0, #0x464] @ S5PC110_CLK_IP1
/* CLK_IP2 */
ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
@ HOSTIF[10] HSMMC0[16]
@ HSMMC2[18] VIC[27:24]
str r1, [r0, #0x468] @ S5PC110_CLK_IP2
/* CLK_IP3 */
ldr r1, =0x8eff038c @ I2C[8:6]
@ SYSTIMER[16] UART0[17]
@ UART1[18] UART2[19]
@ UART3[20] WDT[22]
@ PWM[23] GPIO[26] SYSCON[27]
str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
/* CLK_IP4 */
ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
str r1, [r0, #0x470] @ S5PC110_CLK_IP3
/* wait at least 200us to stablize all clock */
mov r2, #0x10000
1: subs r2, r2, #1
bne 1b
mov pc, lr
internal_ram_init:
ldr r0, =0xF1500000
ldr r1, =0x0
str r1, [r0]
mov pc, lr
/*
* uart_asm_init: Initialize UART's pins
*/
uart_init:
/* set GPIO to enable UART0-UART4 */
mov r0, r8
ldr r1, =0x22222222
str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
ldr r1, =0x00002222
str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
2.关中断
这部分简单，不用改，有兴趣的自己去研究
3.初始化系统时钟
先总结下思路：分三步。第一，设置系统时钟分频比(CLK_DIV0)；第二，设置所有锁相环（PLL）；第三，设置时钟源（mux），这一步必须放最后，这相当于一个总开关。为什么你应该想得到？。
我们要配置的目标时钟是datasheet推荐的：
然后根据datasheet的下面这幅图去配置：
要配置ARMCLK=1000MHz，24MHz(时钟源设为XUSBXTI)时钟源通过APLL（设置pms=3：125：1）提升到FOUTapll=1000MHz，MUXapll设为1，MUXmsys设为0，DIVapll（这个是分频，就是降频的倍数）设为1，还是1000MHz输出，这样就得到了ARMCLK为1000MHz。
其他几个的配置类似的，我图上已经标出来了。
下面演示下相应的寄存器如何配置：
直接看图：
设置分频比 CLK_DIV0=0x14131440
设置锁相环：APLL,MPLL,EPLL,VPLL
注意：设置锁相环之前必须lock time，配置的依据是datasheet中的下图的部分
lock time怎么计算呢？后面的值是代表多少个时钟周期，从前面的图可知apll的时钟源是24MHz，30us要多少个时钟周期呢？30us*24MHz=720=0x2D0
另外几个手册上说需要300和3000周期。怕麻烦的话设最大也行。其他几个我们就设为最大值0xBB8。
开始配置APLL，设置APLL_CON0=0x807D0301
其他几个PLL的配置类似，可以自己去配置，这里就部多说了。
配置mux
根据前面的的图我勾出来的圈圈，应该不难设置，如下图：配置CLK_SRC0=0x10001111
配置好后，等待200us让时钟平稳运行。
修改后的时钟部分代码如下：
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
/* Set Clock divider */
ldr r1, =0x14131440 @
str r1, [r0, #0x300]
/* Set Lock Time */
ldr r1, =0x2D0 @ Locktime : 30us
str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
ldr r1, =0xBB0 @ Locktime : 0xBB8 = 3000
str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
/* S5PC110_APLL_CON */
ldr r1, =0x807D0301 @ 800MHz
str r1, [r0, #0x100]
/* S5PC110_MPLL_CON */
ldr r1, =0x829B0C01 @ 667MHz
str r1, [r0, #0x108]
/* S5PC110_EPLL_CON */
ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
str r1, [r0, #0x110]
/* S5PC110_VPLL_CON */
ldr r1, =0x806C0603 @ 54MHz
str r1, [r0, #0x120]
/* Set Source Clock */
ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
/* wait at least 200us to stablize all clock */
mov r2, #0x10000
1: subs r2, r2, #1
bne 1b
mov pc, lr
然后将 bl sytem_clock_init 放到bl uart_init 前。
下一篇将初始化串口。。。。。