wrHDL编译中软核代码初始化及编译耗时长的问题

问题的提出
整个WR的ISE工程比较大，编译时间很长，导致开发效率低。通过分析发现，ISE在综合的时候大量的时间都花在了初始化DPRAM上。调研发现Xilinx提供了BMM文件和DATA2MEM工具，可以将软核CPU的运行代码在HDL综合完后再与bit文件合并，这样可以节约大量的编译时间。但是在wr工程中使用这些工具的时候出现了错误，软核的代码并没有被成功初始化。

原始代码分析
具体编译wr工程的时候发现，代码ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd中存在对有无RAM初始化文件进行判断，进而采用了不同的调用DPRAM的方法。
其具体实现如下：

GEN_INITF: if g_init_file /= "" and g_init_file /= "none" generate
U_DPRAM : generic_dpram
generic map(
-- standard parameters
g_data_width => ,
g_size => g_size,
g_with_byte_enable => true,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_init_file,
g_dual_clock => false
)
port map(
rst_n_i => rst_n_i,
-- Port A
clka_i => clk_sys_i,
bwea_i => s_bwea,
wea_i => s_wea,
aa_i => slave1_in.adr(f_log2_size(g_size)- downto ),
da_i => slave1_in.dat,
qa_o => slave1_out.dat,
-- Port B
clkb_i => clk_sys_i,
bweb_i => s_bweb,
web_i => s_web,
ab_i => slave2_in.adr(f_log2_size(g_size)- downto ),
db_i => slave2_in.dat,
qb_o => slave2_out.dat
);
end generate;

GEN_NO_INITF: if g_init_file = "" or g_init_file = "none" generate
GEN_BYTESEL: for i in  to  generate
U_DPRAM: generic_dpram
generic map(
g_data_width => ,
g_size => g_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => "",
g_dual_clock => false)
port map(
rst_n_i => rst_n_i,
-- Port A
clka_i => clk_sys_i,
wea_i => s_bwea(i),
aa_i => slave1_in.adr(f_log2_size(g_size)- downto ),
da_i => slave1_in.dat((i+)*- downto i*),
qa_o => slave1_out.dat((i+)*- downto i*),
-- Port B
clkb_i => clk_sys_i,
web_i => s_bweb(i),
ab_i => slave2_in.adr(f_log2_size(g_size)- downto ),
db_i => slave2_in.dat((i+)*- downto i*),
qb_o => slave2_out.dat((i+)*- downto i*)
);
end generate;
end generate;

当GEN_NO_INITF的时候，原作者采用了一个很取巧的办法来避免ise综合出来block ram的同时生成大量的mux(LUT5)，但此时综合出来RAM模块的形式是1bit(数据位）*16K.

而如果要用BMM的方式来对RAM进行初始化，我们想要的RAM模块的形式是32bit*512. GEN_INITF这部分代码综合出来的结果满足需求。

对于SPEC板而言，他们采用的是PCIe的方法来upload软核的初始化代码，所以他们可以使用他们预先定义的办法来使得elf的文件格式满足前述要求（实际不需要额外的工作即可满足，因为他们是用wishbone总线直接烧写进去的）。

而如果是初始化ram文件，或者采用BMM的方法初始化文件，1bit(数据位）*16K形式的RAM会导致软核代码错误，软核无法工作。

问题结论

为了在cute上面能够更快速的编译，采用无RAM的方式，所以需要将判断语句及GEN_NO_INITF部分的代码全都注释掉。

另外，附上注释后cute的bmm文件,在工程项目中加入bmm文件后会随着工程的编译生成*_bd.bmm文件，之后使用data2mem工具将elf文件和bit文件进行合并。

data2mem -bm ../../elf/cutewr_bd.bmm -bd ../../elf/wrc.elf -bt cutewr.bit -o b cutewr_wrc.bit

/* FILE : cutewr.bmm
*  Define a BRAM map for the LM32 memory "xwb_dpram".
*  Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
*  attached to the ISE Project) to find out that there are 46 ramloops and each RAMB16
*  Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
*        Define ramloop 45 downto 0 and databits 31 downto 0 !!! Otherwise the memory
*        content will be swapped and the program fails to execute. Aperently the ramloop
*        number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory "xwb_dpram"
* g_dpram_size = 131072/4
* 64 stacks of size 2048 bytes is 131072 bytes
*
****************************************************************************************/

ADDRESS_SPACE lm32_wrpc_memory RAMB16 [0x00000000:0x0001FFFF]
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram21 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram22 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram23 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram24 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram25 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram26 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram27 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram28 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram29 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram30 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram31 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram32 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram33 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram34 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram35 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram36 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram37 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram38 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram39 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram40 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram41 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram42 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram43 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram44 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram45 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram46 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram47 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram48 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram49 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram50 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram51 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram52 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram53 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram54 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram55 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram56 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram57 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram58 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram59 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram60 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram61 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram62 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram63 [:];
  END_BUS_BLOCK;
  BUS_BLOCK
    U_WR_CORE/U_WR_CORE/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram64 [:];
  END_BUS_BLOCK;
END_ADDRESS_SPACE;