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文件名称:US Navy VHDL Modelling Guide1
文件大小:189KB
文件格式:PDF
更新时间:2014-04-02 09:42:58
A VHDL Modeling Guide
This document was developed under the Standard Hardware and Reliability Program (SHARP) Technology
Independent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC Hardware
Description Language (VHDL) design engineers and is offered as guidance for the development of VHDL models
which are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be provided
to manufacturing engineering personnel for the development of production data and the subsequent production
of hardware. Most VHDL modeling performed to date has been concentrated at either the component level or
at the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under the
SHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon low
complexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quite
simple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assembly
types and complexities.